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Ms. L Babitha

 
IARE10719
Ms. L Babitha
Monday, July 21, 1986
Assistant Professor
1 Years, 9 Months, 9 Days.
12 Years, 5 Months, 6 Days.
Electronics and Communication Engineering
babitha.l@iare.ac.in
9985751631
Full Time
76150404150517
1-7403074817
Digital and Analog Communications, Microprocessors, VLSI Design.
B.Tech (ECE), 2007
M.Tech (Digital Electronics and Communication Systems), 2009
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Google Scholar ID Youtube Link

PDC (Pulse and Digital Circuits), EDC (Electronic Devices and Circuits), MPI (Microprocessors and Interfacing), STLD (Switching Theory and Logic Design), VLSI Design, Satellite Communications.

 

1. A Paper titled “ANALYSIS OF CLOCKFEEDTHROUGH ERROR REDUCTION IN CMOS ANALOG AND DIGITAL CIRCUITS AT 180 nm TECHNOLOGY NODE” published in an International Journal of Pure and Applied Mathematics Volume 120 No. 6 2018, 7825-7837 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ Special Issue.

2. A paper titled “500nW A LOW POWER SWITCHED CAPACITOR BASED ACTIVE LOW PASS FILTER FOR BIOMEDICAL APPLICATIONS” published in an International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016DOI : 10.5121/vlsic.2016.7603 25.

3. A paper titled “A LOW POWER DBI BASED CRC DESIGN USING GDITECHNOLOGY” published in anInternational Conference on Communications, Signal Processing, Computing and Information Technologies (ICCSPCIT-2016) ISBN: 978 93 83038 45 9 Malla Reddy College of Engineering and Technology (Autonomous).

4. A paper titled “ESTIMATION OF LEAKAGE POWER IN CMOS DIGITAL CIRCUITSTACKS” publishedin anInternational Journal Of Technical & Scientific Research -Vol.2, Issue .1 ISSN Online: 2319-9245.

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